The Compute Bottleneck Nobody Talks About

Everyone argues about whether AI scaling will hit a data wall or a power wall. Dylan Patel thinks they are looking at the wrong constraint. The binding limit is semiconductor supply — specifically, how many EUV lithography tools ASML can ship and how much HBM Samsung and SK Hynix can produce. Everything else is a downstream consequence.

The 200GW ceiling

Patel's core claim: total AI chip output is physically capped by EUV tool production. ASML ships a finite number of High-NA machines per year. That number, divided across Nvidia, Google, AMD, and Intel, sets a hard ceiling on global AI compute capacity. His estimate is roughly 200GW of deployed AI compute by the end of the decade — not because demand stops, but because the tools to make the chips cannot scale faster.

This matters for model economics in a direct way. If compute supply is inelastic, then every lab is bidding against every other lab for the same finite wafer starts. The price of intelligence stays high not because algorithms are expensive, but because silicon is scarce.

Hopper vs Blackwell: 20x, not 2x

The raw FLOPS gap between Hopper (H100) and Blackwell (B200) is 2-3x on paper. But Patel points out that for real inference workloads at production token rates, the performance difference is far larger.

"When you look at inference at 100 tokens a second for DeepSeek and Kimi K2.5, the performance difference between Hopper and Blackwell is on the order of 20x." — [Dylan Patel, 62:06](https://www.youtube.com/watch?v=mDG_Hx3BSUE&t=3726)

Twenty times. Not two or three. The reason is that inference at high throughput is not a FLOPS problem — it is a memory bandwidth and networking problem. Blackwell's HBM3e and NVLink5 architecture removes bottlenecks that choke Hopper at serving speed. For labs running large MoE models, this is the difference between a cluster that earns money and one that burns it.

GPT-5.4 is smaller than you think

One of the more counterintuitive points: GPT-5.4 uses fewer active parameters than GPT-4, despite being the stronger model.

"GPT-5.4 is both way cheaper to run than GPT-4 and has fewer active parameters. It is much smaller in active parameters because it is a sparser MoE versus GPT-4 being a coarser MoE." — [Dylan Patel, 14:42](https://www.youtube.com/watch?v=mDG_Hx3BSUE&t=882)

This is an architectural response to the compute constraint. When chips are scarce, you design models that extract more intelligence per FLOP. Sparse MoE is not just a research choice — it is an economic one. The same H100 fleet running GPT-5.4 today is more productive per GPU than when it was running GPT-4 two years ago.

The Anthropic pricing puzzle

Patel also addresses a question [benchmark.space](https://benchmark.space) readers ask constantly: why does [Claude Opus 4.6](https://benchmark.space/model/claude-opus-4.6) cost what it does?

"Anthropic could actually release a slow mode. They could reduce the price of Opus 4.6 by 4-5x and reduce the speed by maybe just 2x." — [Dylan Patel, 77:59](https://www.youtube.com/watch?v=mDG_Hx3BSUE&t=4679)

The implication is that Anthropic's pricing reflects compute scarcity, not model cost. They are allocation-constrained, not margin-constrained. Running Opus 4.6 slower on existing HBM would free up significant capacity — but selling it cheaper does not help when demand already exceeds supply. The rational move is to price at what the market bears, which is exactly what they are doing.

Memory: the hidden tax

Thirty percent of Big Tech AI capital expenditure now goes to memory, not logic. HBM prices have tripled. Smartphone DRAM volumes are projected to drop from 1.1 billion units to 500-600 million as foundries divert capacity to AI-grade memory. The consumer electronics industry is literally shrinking so that AI data centers can expand.

This is a second-order constraint that most coverage ignores. You cannot run a frontier model without HBM, and HBM comes from exactly two suppliers. If Samsung or SK Hynix hits a yield issue, every lab's deployment timeline slips — regardless of how many GPUs Nvidia ships.

Google's quiet advantage

"Google does deploy the largest production model of any of the major labs with Gemini Pro. It is a larger model than GPT-5.4. It is a larger model than Opus." — [Dylan Patel, 132:49](https://www.youtube.com/watch?v=mDG_Hx3BSUE&t=7969)

Google can afford to run the largest model because they control their own silicon. TPU fleets are unipolar — designed around a single architecture for a single customer. There is no multi-tenant inefficiency, no GPU repartitioning between customers. Google trades flexibility for utilization, and at the frontier, utilization wins.

The takeaway

The AI scaling debate focuses on algorithms and data. Those matter. But the physical supply chain — ASML's tool output, HBM fab yields, wafer start allocations — sets the ceiling on how much intelligence the world can produce. Labs that understand this design sparser models, optimize for memory bandwidth, and price at scarcity rather than cost. Labs that do not will find themselves bidding for compute they cannot afford to run models they cannot deploy. The bottleneck is not in the data center. It is in the fab.

Metric	Hopper (H100)	Blackwell (B200)
Theoretical FLOPS advantage	1x (baseline)	2-3x
Real inference advantage at 100 tok/s	1x (baseline)	~20x
Binding constraint	Memory bandwidth + networking	Largely solved